AIM:
Simulation and verification of XOR logic gates.
PROGRAM:
Library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(a,b:in bit;y:out bit);
end xor2;
architecture xor2 of xor2 is
begin
y<=a xor b ;
end xor2;
SIMULATION OUTPUT:
RESULT:
XOR gate is simulated and verified
0 comments
Post a Comment