AIM:
Simulation and verification of OR gate.
PROGRAM:
Library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(a,b:in bit;y:out bit);
end or2;
architecture or2 of or2 is
begin
y<=a or b;
end or2;
SIMULATION OUTPUT:
RESULT:
OR gate is simulated and verified.
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