AIM:

Simulation and verification of NAND gate.

PROGRAM:

Library ieee;
use ieee.std_logic_1164.all;

entity nand2 is
        port(a,b:in bit;y:out bit);
end nand2;

architecture nand2 of nand2 is
begin
        y<=a nand b;
end nand2;

SIMULATION OUTPUT:

 
RESULT:
NAND gate is simulated and verified.

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