AIM:
Simulation and Verification of AND Gate.
PROGRAM:
Library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(a,b:in bit;y:out bit);
end and2;
architecture and2 of and2 is
begin
y <= a and b;
end and2;
SIMULATION OUTPUT:
RESULT:
AND gate is simulated and verified
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