Design and Verify Full Subtractor by using Dataflow Style

AIM:

Design and verify full subtractor by using dataflow style .

PROGRAM:

library ieee;

use ieee.std_logic_1164.all;

entity fs1 is

        port(a,b,c:in bit;d,bo:out bit);

end fs1;

architecture fs1 of fs1 is

begin

        d<=a xor b xor c;

        bo<=((not a)and b)or(b xor c);

end fs1;

SIMULATION OUTPUT:

RESULT:

Full subtractor is simulated and verified