Design and Verify Half Subtractor by using Dataflow Style

AIM:

Design and verify half subtractor by using dataflow style .

PROGRAM:

Library ieee;

use ieee.std_logic_1164.all;

entity hs1 is

        port(a,b:in bit;d,bo:out bit);

end hs1;

architecture hs1 of hs1 is

begin

        d<=a xor b;

        bo<=(not a) and b;

end hs1;

SIMULATION OUTPUT:

 

RESULT:

Half subtractor is simulated and verified