Design and Verify Full Subtractor by Using Dataflow Style with Select Statement

AIM:
Design and verify full subtractor by using dataflow style with select statement.

PROGRAM:

library ieee;

use ieee.std_logic_1164.all;

entity flsub_select is

            port(a:in bit_vector(2 downto 0);

                    s:out bit_vector(1 downto 0));

end flsub_select;

architecture beh of flsub_select is

begin

            with a select

                        s<=("00") when "000",

                        ("11") when "001",

                        ("11") when "010",

                        ("01") when "011",

                        ("10") when "100",

                        ("00") when "101",

                        ("00") when "110",

                        ("11") when "111";

end beh;

SIMULATION OUTPUT:

 

RESULT: 

Full subtractor using dataflow style with select statement is simulated and verified.