Design and Verify Full Adder by using Dataflow Style

AIM:

Design and Verify Full Adder by using Dataflow Style .

PROGRAM:

Library ieee;

use ieee.std_logic_1164.all;

entity fa1 is

            port(a,b,c:in bit;s,cout:out bit);

end fa1;

architecture fa1 of fa1 is

begin

            s<=a xor b xor c;

            cout<=(a and b)or(a and c)or (b and c);

end fa1;

SIMULATION OUTPUT:

 

RESULT: Full adder is simulated and verified