Simulation and verification of NOR gate

AIM:

Simulation and verification of NOR gate.

PROGRAM:

library ieee;

use ieee.std_logic_1164.all;

entity nor2 is

        port(a,b:in bit;y:out bit);

end nor2;

architecture nor2 of nor2 is

begin

        y<=a nor b;

end nor2;

SIMULATION OUTPUT:

 

RESULT:

NOR gate is simulated and verified.