Design and Verify Full Subtractor by Using Behavioural Model with if,elsif & then Statements

AIM:

Design and verify full subtractor by using behavioural model with if,elsif & then
statements.

PROGRAM:

library ieee;

use ieee.std_logic_1164.all;

entity fullsub is

            port(a:in std_logic_vector(2 downto 0);

                    d,b:out std_logic);

end fullsub;

architecture fullsub of fullsub is

begin

            process(a)

            begin

                        if a="000" then d<='0';b<='0';

                        elsif a="001" then d<='1';b<='1';

                        elsif a="010" then d<='1';b<='1';

                        elsif a="011" then d<='0';b<='1';

                        elsif a="100" then d<='1';b<='0';

                        elsif a="101" then d<='0';b<='0';

                        elsif a="110" then d<='0';b<='0';

                        else d<='1';b<='1';

                        end if;

            end process;

end fullsub;

SIMULATION OUTPUT:

RESULT: Full adder is simulated and verified